The present invention relates to a semiconductor device structure, and in particular, but not exclusively, to a power semiconductor device structure.
In the technology of integrated circuits of the mixed type, the signal control or processing circuits together with the power transistors capable of driving loads at high voltage and/or high current are integrated on the same chip of semiconductor material. The transistors of the control circuitry are low-voltage transistors, with a collector-base, open emitter breakdown voltage (BVcbo) which is typically between 20 and 50 V. The power transistors have a breakdown voltage generally greater than 50 V and withstand maximum currents between a few hundredths of a milliampere and a few tens of amperes. An example of a technology of integrated circuits of the mixed type is the VIPower technology (VIPower is a trade mark of SGS-Thomson Microelectronics S.r.l.), described, for example, in European Patent Application EP-322040 filed by SGS-Thomson Microelectronics S.r.l.
In certain applications it is necessary to have PNP-type power transistors, for example, in applications of the xe2x80x9chigh side driverxe2x80x9d type, in which the emitter terminal of the PNP power transistor is connected to the positive terminal of a power source (V d.c.), while the collector terminal drives a load having the other terminal connected to a reference terminal (earth or ground) which is connected to the negative terminal of the power source.
An example of a PNP transistor made with VIPower technology and usable in such a configuration is described in xe2x80x9cVertical PNP transistors for Power ICs in high side driver applicationsxe2x80x9d, R. Zambranoxe2x80x94ENE-MAUEN, Florence, 1991. Technologies of the mixed type in the known art impose an upper limit on the maximum voltage applicable to PNP power transistors. The breakdown voltage of PNP power transistors is generally less than 100 V, which considerably restricts the range of application of known devices.
This disadvantage of the known art of imposing an upper limit or the maximum voltage applicable to power transistors is avoided by the present invention. The present invention provides a structure of a power semiconductor device comprising at least one PNP power transistor and control circuitry of the PNP power transistor. The structure is formed in a chip of semiconductor material comprising, between a first and a second surface, an N-type substrate and an N-type epitaxial layer, and is characterized in that it comprises at least a first P-type region comprising a first buried region between the substrate and the epitaxial layer, and a first contact region extending from the second surface to the first buried region. The first region and the second surface delimit a first portion of the epitaxial layer containing the control circuitry. At least one second P-type region comprising a second buried region between the substrate and the epitaxial layer and a second contact region extends from the second surface to the second buried region. The second region and the second surface delimit a second portion of the epitaxial layer. A third P-type region extends from the second surface to the interior of the second portion of the epitaxial layer. The second region, the second portion of the epitaxial layer and the third region contain, respectively, the collector, base and emitter regions of the PNP power transistor. This structure may be used to make a vertical current-conducting PNP power transistor having a high breakdown voltage, typically greater than 200 V.
The structure according to the present invention also offers the advantage, for example with respect to the structures formed with the VIPower technology, of using a single epitaxial layer, with a consequently greater simplicity of the corresponding manufacturing process. The process according to the present invention makes it possible to form in a simple way a plurality of PNP power transistors integrated on the same chip and fully insulated electrically from each other. This makes it possible to form different power stages, with a plurality of independent terminals, on the same chip.